Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips

Conference: CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications
08/23/2016 - 08/25/2016 at Dresden, Deutschland

Proceedings: CNNA 2016

Pages: 2Language: englishTyp: PDF

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Carmona-Galan, Ricardo; Fernandez-Berni, Jorge; Rodriguez-Vazquez, Angel (Instituto de Microelectronica de Sevilla (IMSE-CNM), CSIC-Universidad de Sevilla, Spain)

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementation.