Real time architectures for the Scale Invariant Feature Transform algorithm
Conference: CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications
08/23/2016 - 08/25/2016 at Dresden, Deutschland
Proceedings: CNNA 2016
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Domenech-Asensi, G.; Garrigos, J. (Dpto. de Electrónica, Tec. de Computadoras y Proyectos, Universidad Politécnica de Cartagena, Cartagena, Spain)
Lopez, P.; Brea, V.; Cabello, D. (Centro de Inv. en Tecnoloxias da Informacion (CITIUS), University of Santiago de Compostela, Santiago de Compostela, Spain)
Feature extraction in digital image processing is a very intensive task for a CPU. In order to achieve real time image throughputs, hardware parallelism must be exploited. The speed-up of the system is constrained by the degree of parallelism of the implementation and this one at the same time, by programmable device size and the power dissipation. In this work, issues related to the synthesis of the Scale-Invariant Feature Transform (SIFT) algorithm on a FPGA to obtain target processing rates faster than 50 frames per second for VGA images, are analyzed. In order to increase the speedup of the algorithm, the work includes the analysis of feasible simplifications of the algorithm for a tracking application and the results are synthesized on an FPGA.