3D Technologies for massive parallel computing vision systems: Expected Performances, Design Constraints and Trends
Conference: CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications
08/23/2016 - 08/25/2016 at Dresden, Deutschland
Proceedings: CNNA 2016
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Sicard, Gilles; Millet, Laurent; Vigier, Margaux (Université Grenoble Alpes, 38000 Grenoble, France & CEA, LETI, MINATEC Campus, 38054 Grenoble, France)
Chevobbe, Stephane (CEA, LIST, Gif-Sur-Yvette, 91191, France)
Nowadays, most microelectronic companies develop technologies to stack several silicon dies. These circuits have to be connected together and two main ways are developing: TSV (Trough Silicon Via) or face to face bonding. As the microelectronic evolution, the pitch of this intra die connection decreases continuously and the current value is around 10micrometer. For a vision system point of view, this value opens the way to a point to point connection between the photosensitive pixel and a “computing element”. This element (analog, or digital, or both) can have the same pitch than the imager pixel or a bigger pitch for a cluster of digital processing elements for example. Unfortunately, this 3D connection implies some design constraints due to the final power consumption, thermal problem, and floorplanning limitations. This paper discusses about these promising kind of architectures, their design constraints and their physical limitations. Two 3D chips under fabrication will be presented as case studies.