Algorithmic Considerations in Memristive Memory Processing Units (MPU)
Conference: CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications
08/23/2016 - 08/25/2016 at Dresden, Deutschland
Proceedings: CNNA 2016
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Hur, Rotem Ben; Talati, Nishil; Kvatinsky, Shahar (Andrew & Erna Viterbi Faculty of Electrical Engineering – Technion – Israel Institute of Technology, Haifa 3200003, Israel)
Memristive technologies are attractive candidates to replace conventional memory technologies, and can also be used to perform logic and arithmetic operations using a technique called 'stateful logic.' Combining data storage and computation in the memory array enables a novel non-von Neumann architecture, where both the operations are performed within a Memory Processing Unit (MPU). The use of an MPU alleviates the primary restriction on performance and energy in von Neumann machine, which is the data transfer between CPU and memory. To optimize the speed, energy, and area efficiency of the MPU, different algorithms need to be developed. This paper discusses the considerations in setting the sequence of computing operations in an MPU and presents examples of two operations that can benefit from processing within memristive memory.