Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis

Conference: FSP 2016 - Third International Workshop on FPGAs for Software Programmers
08/29/2016 at Lausanne, Schweiz

Proceedings: Third International Workshop on FPGAs for Software Programmers (FSP 2016)

Pages: 11Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Brugnoni, Silvano; Corbat, Thomas; Sommerlad, Peter; Suter, Toni (IFS Institute for Software, FHO HSR Hochschule für Technik Rapperswil, Switzerland)
Korinth, Jens; Chevallerie, David de la; Koch, Andreas (Embedded Systems and Applications Group (ESA), TU Darmstadt, Germany)

Despite the advances in high-level hardware synthesis (HLS), the programming style required by the design tools for generating efficient hardware implementations still differs significantly from that used in conventional software development. To ease the development of high-quality hardware accelerators using HLS, we propose the use of automated interactive source code transformations. Guided by the user, the transformations help to avoid much of the tedious and potentially error-prone manual code re-development process. The automation also takes aspects of the system-on-chip architecture into account, e.g., addressing data-movement and the creation of heterogeneous pools of processing elements, which can then be accessed in a multi-threaded manner from software. We demonstrate the technique targeting both reconfigurable systems-on-chip, as well as PCIe Gen3-attached compute platforms.