Transparent Live Code Offloading on FPGA
Conference: FSP 2016 - Third International Workshop on FPGAs for Software Programmers
08/29/2016 at Lausanne, Schweiz
Pages: 10Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Rigamonti, Roberto; Delporte, Baptiste; Convers, Anthony; Dassatti, Alberto (HES-SO REDS Institute, HEIG-VD—School of Business and Engineering Vaud, 1400 Yverdon-les-Bains, Switzerland)
Even though it seems that FPGAs have finally made the transition from research labs to the consumer devices’ market, programming them remains challenging. Despite the improvements made by High-Level Synthesis (HLS), which removed the language and paradigm barriers that prevented many computer scientists from working with them, producing a new design typically requires at least several hours, making data- and context-dependent adaptations virtually impossible. In this paper we present a new framework that off-loads, on-the-fly and transparently to both the user and the developer, computationally-intensive code fragments to FPGAs. While the performance should not surpass that of hand-crafted HDL code, or even code produced by HLS, our results come with no additional development costs and do not require producing and deploying a new bit-stream to the FPGA each time a change is made. Moreover, since optimizations are made at run-time, they may fit particular datasets or usage scenarios, something which is rarely foreseeable at design or compile time. Our proposal revolves around an overlay architecture that is pre-programmed on the FPGA and dynamically reconfigured by our framework to execute code fragments extracted from the Data Flow Graph (DFG) of computational intensive routines. We validated our solution using standard benchmarks and proved we are able to off-load to FPGAs without developer’s intervention.