An interactive environment for mapping computational structures to FPGAs
Conference: FSP 2016 - Third International Workshop on FPGAs for Software Programmers
08/29/2016 at Lausanne, Schweiz
Pages: 3Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Wester, Rinse; Groote, Robert de (Computer Architecture for Embedded Systems, University of Twente, The Netherlands)
In this paper we propose a methodology to translate computational structures to hardware. Computational structures express both the computation and the ordering of computations. These structures are expressed using dataflow graphs from which hardware can be generated more directly compared to imperative approaches. As a proof of concept, SDFkit is developed. SDFkit is a cycle accurate simulation and development environment for these computational structures. Additionally, SDFkit has a code generation backend to generate FPGA code.