Impact of Temperature Imbalance on Junction Temperature Identification for Multiple Chip Modules Using TSEPs

Abstract:
Junction temperature sensing using Temperature Sensitive Electrical Parameters (TSEPs), like the forward voltage at low currents, is a technique widely used for identifying the degradation of the thermal impedance during power cycling tests. SiC devices are now widely commercially available, however, there are two factors which characterize the use of TSEPs for temperature sensing in SiC, namely (i) a smaller chip size, which requires multiple parallel chips for enabling higher current modules and (ii) a reduced temperature sensitivity due to the wide bandgap characteristics. Moreover, since parallel connected chips may not degrade uniformly, junction temperature variation can result in parallel chips with different junction-to-case thermal resistances. In this case, assuming an average junction temperature for the paralleled chips can give erroneous estimations depending on the magnitude of the junction temperature difference. When there is low temperature imbalance between the parallel devices, the global TSEP is an accurate indicator, however, as the temperature imbalance increases, it underestimates the temperature of the hotter device.