Current Control Delay Reduction for FPGA-Based Servodrive

Abstract:
The parallel processing power of an FPGA along with model-based control strategies enables ultimate performance of a servo drive in terms of tracking precision and control bandwidth. Oversampling of the current reference vector in modern systems enables new control techniques boosting servo drive performance. The dynamic model oversampled current control approach with regular current feedback sampling presented in the paper enables the significant decrease in the current control delay time. It features the time-discrete fixed step model control enabled by regular current feedback sampling with the realization on FPGA. The simulation and experimental results showed significant Bode plot phase characteristics improvement of the digital closed-loop current control. The results were obtained from a state of art industrial direct servo drive with 8 kHz PWM-controlled IGBT inverter coupled with either linear and rotary PMSMs. The resulting current control bandwidth significantly exceeded 4 kHz. The technique is especially effective in the case of high current reference oversampling rates and medium to low PWM inverter output voltage levels.