A Case for Better Integration of Host and Target Compilation When Using OpenCL for FPGAs

Conference: FSP 2017 - Fourth International Workshop on FPGAs for Software Programmers
09/07/2017 at Ghent, Belgium

Proceedings: Fourth International Workshop on FPGAs for Software Programmers (FSP 2017)

Pages: 9Language: englishTyp: PDF

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Authors:
Lloyd, Taylor; Chikin, Artem; Ochoa, Erick; Ali, Karim; Nelson Amaral, Jose (University of Alberta, Edmonton, Canada)

Abstract:
Major Field-Programmable Gate Array (FPGA) vendors, such as Intel and Xilinx, provide toolchains for compiling Open Computing Language (OpenCL) to FPGAs. However, the separate host and device compilation approach advocated by OpenCL hides compiler optimization opportunities that can dramatically improve FPGA performance. This paper demonstrates the advantages of combined host and device compilation for OpenCL on FPGAs by presenting a series of transformations that require inter-compiler communication. Further, because of extremely long FPGA synthesis times, the overhead of recompiling the host code for each compilation of FPGA kernel code is relatively inexpensive. Our transformations are integrated with the Intel FPGA SDK for OpenCL and are evaluated on a subset of the Rodinia benchmark suite using an Altera Stratix V FPGA.