PCIeHLS: an OpenCL HLS framework
Conference: FSP 2017 - Fourth International Workshop on FPGAs for Software Programmers
09/07/2017 at Ghent, Belgium
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Vespera, Malte; Kocha, Dirk; Phama, Khoa (University of Manchester, United Kingdom)
One of the goals of high level synthesis (HLS) is to make designing hardware accelerators running on FPGAs accessible to developers with a software background (usually implying developers with little foundations in hardware design). While high level synthesis generates accelerator kernels, it generally does not assist with integrating the generated kernels into a system. In this paper we introduce PCIeHLS, a framework which helps in providing the required infrastructure consisting of memory, PCIe interface, ICAP for partial reconfiguration, and clock managers. PCIeHLS provides several partial regions, allowing to load multiple modules at the same time. Consequently, multiple kernels can be used simultaneously for multi threading or to run several independent applications. Moreover, regions can be combined to host larger accelerators and accelerators can be relocated at the bitstream level.