Spatial Memory Trace Prediction

Conference: FSP 2017 - Fourth International Workshop on FPGAs for Software Programmers
09/07/2017 at Ghent, Belgium

Proceedings: Fourth International Workshop on FPGAs for Software Programmers (FSP 2017)

Pages: 10Language: englishTyp: PDF

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Authors:
Gebara, Nadeen Yassir (Intel Corporation, Hudson, MA, USA & EPFL, Lausanne, Switzerland)
Ienne, Paolo; Fleming, Kermin (EPFL, Lausanne, Switzerland)

Abstract:
Heterogeneous FPGA systems among other spatial architectures are gaining popularity as candidates for accelerating Data Center and HPC applications. As the number of FLOPs supported on FPGAs increases, the rate at which data can be provided to computational units becomes the major bottleneck determining overall system performance. This heightens the importance of having a quick way to observe and understand the memory access patterns of applications on FPGAs prior to investing long periods of time and effort in writing RTL, especially for applications that will not observe any performance improvements due to bandwidth limitations. Furthermore, since the memory subsystem within FPGAs is programmable, a clear visibility of the spatial memory access patterns of applications prior to design implementation can guide FPGA programmers on the best way to configure and use the memory subsystem in an application specific manner while providing an estimate of bandwidth requirements. In this paper, we present a novel approach for obtaining memory traces of workloads targeting FPGA systems to provide insight on the memory access patterns of applications and guide FPGA programmers. Our algorithm displays an average prediction accuracy of 97.45% for read memory accesses when RTL optimization opportunities are fully exploited, and an accuracy of 90.71% for memory write accesses across the investigated benchmarks. By providing a fast and efficient way to obtain spatial memory reference traces of applications, our work not only guides FPGA programmers by providing more insight into the memory profiles of workload regions amenable to FPGA implementations, but also helps leverage the shortage of memory traces available for performing architectural studies and enhancing FPGA memory systems.