On the HLS Design of Bit-Level Operations and Custom Data Types

Conference: FSP 2017 - Fourth International Workshop on FPGAs for Software Programmers
09/07/2017 at Ghent, Belgium

Proceedings: Fourth International Workshop on FPGAs for Software Programmers (FSP 2017)

Pages: 8Language: englishTyp: PDF

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Authors:
Garcia Ordaz, Jose Raul; Koch, Dirk (School of Computer Science, The University of Manchester, United Kingdom)

Abstract:
Modern high-level synthesis (HLS) tools provide software programmers with a path to accelerate complex processing systems by automating the time-consuming task of generating RTL code. Typically, a HLS tool takes a compute-intensive portion of a software application and produces a functionally equivalent hardware unit. However, in particular for bit-level operations, the coding style used to develop the source code corresponding to a compute-intensive kernel hampers the synthesis of high quality results. In this paper, we explore design guidelines for bit-level operations and custom data types that can help software developers to write HDL-friendly C code in order to automatically produce high quality hardware.