Applying the Ideal Testing Framework to HDL Programs

Conference: ARCS Workshop 2018 - 31th International Conference on Architecture of Computing Systems
04/09/2018 - 04/12/2018 at Braunschweig, Germany

Proceedings: ARCS 2018

Pages: 6Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Kilincceker, Onur; Belli, Fevzi (University of Paderborn, Paderborn, Germany)
Turk, Ercument; Challenger, Moharram (International Computer, Institiute, Ege University, Izmir, Turkey)

This paper proposes a framework for testing behavioral model of sequential circuits implemented in Hardware Description Language (HDL). The concept of Ideal Testing is applied for achieving reliability and validity of both positive and negative testing. The HDL program is first modeled by a Finite State Machine (FSM) which is then converted to a Regular Expression (RE). This RE is used to construct test sequences. For positive testing, the original (fault-free) FSM model is used, while for negative testing its mutant model(s) are used to define requirements of ideal testing in conjunction with model-based and code-based mutation testing. A demonstrating example based on a real-life-like Traffic Light Controller (TLC) validates the proposed approach and analyzes its characteristic features.