Reverse Engineering the Timing Parameters of the I/O-System in Microcontrollers
Conference: ARCS Workshop 2018 - 31th International Conference on Architecture of Computing Systems
04/09/2018 - 04/12/2018 at Braunschweig, Germany
Proceedings: ARCS 2018
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Seifert, Georg; Hiergeist, Sebastian (Technische Hochschule Ingolstadt, Ingolstadt, Germany)
In safety-critical real time systems, one of the challenges is to determine the upper bound of the execution time of the application. Currently, static Worst Case Execution Time (WCET) analyses are used for this purpose, which need exact knowledge of the processors. Due to the increasing number of peripherals and corresponding traffic within a Microcontroller Unit (MCU), CPU-focused analysis will no longer be sufficient in the future. As a result, the knowledge must be extended to the entire MCU. As manufacturers do not provide this information due to know-how protection, it must be obtained through detailed analyses. This article presents an analysis method based on microbenchmarks that provides the relevant timing and architectural information and shows how to prepare this knowledge for a subsequential WCET analysis.