Derating of Parallel SiC MOSFETs Considering Switching Imbalances
Conference: PCIM Europe 2018 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
06/05/2018 - 06/07/2018 at Nürnberg, Deutschland
Proceedings: PCIM Europe 2018
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Bertelshofer, Teresa; Maerz, Andreas; Bakran, Mark-M. (University of Bayreuth, Department of Mechatronics, Center of Energy Technology, Germany)
This paper presents a numerical method used to analyse the parallel connection of several SiC MOSFET dies. Parallel connection is necessary to achieve the desired current carrying capability of main inverters for xEV-drives. With this method the effect of asymmetries within the chips’ parameters, especially the threshold voltage, are investigated. The investigation results quantify to what extent the PTC behaviour of the on-state resistance can mitigate the overheating of one chip caused by switching loss imbalance. The results are used to define the necessary derating of the inverter output power, so that no single chip is thermally overstressed.