Improved Parallelization of Legacy Embedded Software on Soft-Core MPSoCs through Automatic Loop Transformations
Conference: FSP Workshop 2018 - Fifth International Workshop on FPGAs for Software Programmers
08/31/2018 at Dublin, Ireland
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Heid, Kris; Wenzel, Jakob; Hochberger, Christian (Computer Systems Group, Technische Universität Darmstadt, Merckstr. 25, 64283 Darmstadt, Germany)
Today, a growing number of digital systems containing a software part is realized on Field Programmable Gate Arrays. This allows to use application specific multi-core architectures to run parts of the application in parallel. Automatic parallelization of embedded software is desired to make optimal use of these flexible multi-core architectures. In many programs, loops hold a majority of the total execution time and benefit from parallelization. In this contribution, we present a loop transformation tool that improves the parallelizability of typical legacy C code containing loops by a factor of two. Different than other approaches, we are using a pipeline-parallel execution model especially suited for distributed-memory systems. This execution model has widely different demands on beneficial loop transformation methods than other well known parallel execution models like widely applied in HPC.