ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications

Conference: FSP Workshop 2018 - Fifth International Workshop on FPGAs for Software Programmers
08/31/2018 at Dublin, Ireland

Proceedings: Fifth International Workshop on FPGAs for Software Programmers (FSP 2018)

Pages: 9Language: englishTyp: PDF

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Pham, Khoa Dang; Vaishnav, Anuj; Vesper, Malte; Koch, Dirk (School of Computer Science, The University of Manchester, Manchester, UK)

In this work, we are proposing the ZUCL framework for implementing and running OpenCL applications for the latest Xilinx ZYNQ UltraScale+ platform. ZUCL is a holistic framework addressing the FPGA OS infrastructure, high level synthesis (HLS) module implementation as well as the runtime management. ZUCL enables partial reconfiguration (PR) on this platform by providing an infrastructure featuring multiple adjacent PR regions having an identical resource layout. This allows users building their hardware modules once but instantiating them multiple times in the provided regions in a hot plug-and-play manner as well as implementing different sized modules that can share the reconfigurable resources. An automatic physical implementation backend based on templates allows implementing OpenCL kernels into hardware modules all the way from OpenCL descriptions to relocatable accelerator bitstreams in a fully software-centric design process. Finally, prototypes of generic device drivers for OpenCL kernels and a hardware task scheduler together with low-level configuration drivers have been developed to manage kernels at runtime. A demonstrator on a Xilinx ZCU102 evaluation board will show how multiple OpenCL kernels can be implemented and executed simultaneously with ease and flexibility by a ZYNQ UltraScale+ platform under direct control of the ARM SoC running Linux.