HatScheT: A Contribution to Agile HLS
Conference: FSP Workshop 2018 - Fifth International Workshop on FPGAs for Software Programmers
08/31/2018 at Dublin, Ireland
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Sittel, Patrick; Kumm, Martin; Zipf, Peter (University of Kassel, Germany)
Oppermann, Julian; Koch, Andreas (Technical University of Darmstadt, Germany)
Today, the design of hardware implementations using FPGAs, SoCs or ASICs is driven by tight project time and cost constraints. Additionally, it is impossible to specify every step and functionality of a complex project beforehand. Therefore, large teams from different areas of expertise, e.g., software, hardware development, system integration, need to work hand in hand as they are confronted with an ever changing environment of specifications. Detailed simulations and prototyping are used to keep track of the project status and for the identification of failed developments as early as possible. Over the recent years, high-level synthesis (HLS) is used more and more for hardware design. Unfortunately, run times can become very long when close to optimal implementations are demanded. It follows that an inflexible HLS design flow is not applicable for large, complex and changing projects. With the open-source C++ scheduling library HatScheT we provide a tool for run time flexible scheduling, which is the most important and time consuming step of HLS. The user of HatScheT is able to chose from a variety of scheduling algorithms, which enables control over a scheduling run time vs. quality tradeoff. Additionally, an adaptive decider program is presented that will automatically chose one from a set of scheduling algorithms based on the size of the input problem. This enables a flexible scheduling flow, where optimal algorithms are applied when a low complexity is identified, while heuristics are chosen for large and time consuming scheduling problems.