A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement
Conference: FSP Workshop 2018 - Fifth International Workshop on FPGAs for Software Programmers
08/31/2018 at Dublin, Ireland
Pages: 9Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Oezkan, M. Akif; Teich, Juergen; Hannig, Frank (Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany)
Perard-Gayot, Arsene (Saarland University (UdS), Germany)
Membarth, Richard; Slusallek, Philipp (Saarland University (UdS), Germany & German Research Center for Artificial Intelligence (DFKI), Germany)
Field Programmable Gate Arrays (FPGAs) are continually improving their computing capabilities and energy efficiency. Yet, programming FPGAs remains a time-consuming task and requires expert knowledge to obtain good performance. Recent advancements in High-Level Synthesis (HLS) promise to solve this problem. However, today’s HLS tools still require vendor-specific low-level optimizations in the form of compiler hints and code restructuring. Despite the pursuit of new programming methodologies for many-core, multi-threading, or vector architectures, the FPGA community mostly tries to improve the design techniques from existing programming languages that are either sequential or developed for other computing platforms. In this paper, we use a state-of-the-art functional language that offers explicit control over code refinement to design border handling circuits. This allows us to produce high-level, elegant code descriptions that can be easily refined to low-level hardware designs. Additionally, these descriptions can be exposed to software developers in the form of either a DSL or library.