Identification of WCET Analysis Parameters for Asynchronous I/O Processing in MCUs
Conference: ARCS Workshop 2019 - 32nd International Conference on Architecture of Computing Systems
05/20/2019 - 05/21/2019 at Copenhagen, Denmark
Proceedings: ARCS 2019
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Seifert, Georg; Schwierz, Andreas (Technische Hochschule Ingolstadt, Ingolstadt, Germany)
The estimation of the upper bound of the execution time is one of the challenges in the analysis for safety-critical real-time applications. Since a long time, the static Worst Case Execution Time (WCET) estimation of single core CPU-focused systems without shared resources is investigated and can now be regarded as solved. The WCET analysis with shared resources is not feasible with current practice due to lack of information about the internal timing of the conflicting components, especially the Input/Output (I/O) system. The rise of system functionality and especially the growth of interfaces with high bandwidth in Microcontroller Units (MCUs), has resulted in a situation where a CPU-only processing of the I/O is not anymore feasible. Therefore, dedicated hardware components, like DMA-Controller (DMAC), have to be considered and disadvantages of conflictafflicted transfers must become part of the analysis. To resolve the problems with interference afflicted MCU internal data transfers, an approach is here presented which describes the influence parameters of the WCET. Afterwards individual parameters are expressed in a simplified model of the MCU. This provides a coherent description of the relationships between each parameter to enable further analysis.