Accelerating Human Activity Recognition Systems on FPGAs through a DSL approach
Conference: FSP Workshop 2019 - Sixth International Workshop on FPGAs for Software Programmers
09/12/2019 at Barcelona, Spain
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Fernandes, Daniel A. P. L. (Faculdade de Engenharia da Universidade do Porto, Porto, Portugal)
Cardoso, Joao M. P. (Faculdade de Engenharia da Universidade do Porto, Porto, Portugal & INESC TEC, Porto, Portugal)
Data analytics is the process of drawing conclusions based on thorough examination of data. It is usually accomplished by machine learning techniques and the algorithms involved must often process large datasets. This severely hurts performance. However, due to the amount of parallel work present in the algorithms, targeting these applications to FPGA-based systems can help in this regard. The problem is the programming model employed by FPGAs. Most software developers have little to no knowledge in hardware description languages (HDLs) and even the currently available high-level synthesis (HLS) tools are difficult to master, as these still require much familiarity with the hardware being targeted. One of the most popular solutions to this problem has been the use of domain-specific languages (DSLs), which have been developed in several domains. This paper presents a new DSL for the data analytics domain, focusing FPGA execution. A human activity recognition (HAR) case study is used to both motivate the development of the DSL and evaluate it. Our results show that HAR systems can be targeted to an FPGA using the developed DSL.