Impact of Off-Chip Memories on HLS-Generated Circuits
Conference: FSP Workshop 2019 - Sixth International Workshop on FPGAs for Software Programmers
09/12/2019 at Barcelona, Spain
Pages: 10Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Rajagopala, Abhi D.; Sass, Ron (Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, Charlotte, NC, USA)
Schmidt, Andrew (Information Sciences Institute, University of Southern California, Arlington, VA, USA)
High-Level Synthesis (HLS) has been proposed as a comfortable high-level programming languages solution to overcome the insurmountable barrier of hardware design and Hardware Description Languages (HDLs). While academic and commercial tools have made huge strides, nearly all of these tools focus exclusively on the computation and the data path. Rarely do they directly address the memory subsystem and its impact on the overall performance. At best, the programmer can assist the tools with directives/pragmas but these are designed to change the data path and only indirectly impact the memory subsystem performance. With introduction of next-generation memories such as HMC, HBM etc. these directives will (unintentionally) exacerbate memory issues. In this we paper, we explore the impact on off-chip memory by designing different kernels with different optimizations. We test these kernels with two different commercial HLS flow on three different platforms consisting DDR3 and DDR4 memory. Based on this sweeping study and the requirements of next-generation memory, we design a hardware-software methodology to improve the off-chip memory access. The results suggest that this is suitable for next-generation memory and a lot opportunity to improve the methodology.