Invited Tutorial: OpenCL design flows for Intel and Xilinx FPGAs: Using common design patterns and dealing with vendor-specific differences
Conference: FSP Workshop 2019 - Sixth International Workshop on FPGAs for Software Programmers
09/12/2019 at Barcelona, Spain
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Kenter, Tobias (Paderborn Center for Parallel Computing and Department of Computer Science, Paderborn University, Paderborn, Germany)
An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In this manuscript, we want to broaden that scope and provide practical guidance for both tool chains. We outline the common underlying design philosophy and goals of high level synthesis for FPGAs on an abstract level, before proceeding to an example-driven discussion of tool features and concepts. We present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs. We outline how tool differences that can be overcome for portability, or used for further optimized tool-specific designs.