Thermal Study on Leadframe Dimensioning for High Power Dissipation and Low Inductance Commutation Cells
Conference: PCIM Europe digital days 2020 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
07/07/2020 - 07/08/2020 at Deutschland
Proceedings: PCIM Europe digital days 2020
Pages: 8Language: englishTyp: PDF
Weimer, Julian; Koch, Dominik; Kallfass, Ingmar (Institute of Robust Power Semiconductor Systems, University of Stuttgart, Germany)
Sharma, Ankit Bhushan; Huesgen, Till (Electronics Integration Lab, Hochschule Kempten, Germany)
The use of packaging technologies, which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.