Voltage Bias Effect on the ESR of Ferroelectric Ceramic Capacitors

Conference: PCIM Europe digital days 2020 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
07/07/2020 - 07/08/2020 at Deutschland

Proceedings: PCIM Europe digital days 2020

Pages: 6Language: englishTyp: PDF

Haag, Hermann; Haemmerle, Florian (Omicron Lab, Austria)
Ben-Yaakov, Shmuel (Ben-Gurion University, Israel)

The effect of DC voltage bias on the ESR of ferroelectric ceramic capacitors was studied experimentally. It was found that the ESR is increasing with capacitor voltage in the range of 5% to 80% over the specified voltage range of the tested components. These results are opposite to the trend displayed by the online simulation tool offered by a ferroelectric ceramic capacitors manufacturer. The implications of the obtained results to the losses of ferroelectric ceramic capacitors used in switched mode power supplies are that the estimated losses and voltage ripple are larger when the capacitors are under voltage bias.