Impact of Threshold Voltage Instabilities of SiC MOSFETs on the Methodology of Power Cycling Tests

Abstract:
When power cycling SiC MOSFETs steep temperature gradients intendedly lead to thermo-mechanical stress degrading the package. The observation of package degradation, however, is impeded by trapping effects in the chip caused by the gate bias. For proper analysis and understanding these superimposed effects need to be separated. For this purpose the electrically induced threshold voltage (Vth) instability has been investigated under gate conditions as in a power cycling test bench and at constant temperature, using devices without package degradation. This way the influence of Vth instability can be identified and consequences for the methodology of power cycling tests derived. Those concern junction temperature sensing, failure indication and separation as well as the induced thermo-mechanical stress. Adjustments are consequently proposed.