Analytical Circuit Model for COSS Losses in SiC Junction Termination Extensions

Abstract:
The development and commercialization of SiC-based power devices have quickly gained attention due to their outstanding electrical and thermal properties, which enables opportunities in high voltage and high-frequency power conversion applications. However, prior literature has characterized numerous commercial SiC devices and discovered significant large-signal off-state COSS charge-voltage hysteresis (namely, COSS loss). The substantial contribution in the COSS loss is originated from charging and discharging conduction losses at the termination of the device. And the dynamic charge imbalance is mainly due to the incomplete ionization effect in doped SiC material. Therefore, this paper proposes an analytical SPICE model to capture the high-frequency COSS loss using process and design parameters for one of the most commonly used edge termination - JTE. The SPICE model provides a method to capture the COSS loss during circuit design and a deeper insight on the future optimization of high-frequency SiC device design.