Research on High Speed and Low Power Comparator Design

Abstract:
This paper is a research on the low power and high speed comparators proposed recent years and discusses several design methods of comparator. An improving latch-type comparator with the dynamic bias technique used in preamplifier stage is proposed to optimize energy consumption. On the contrary, an improved double-tail comparator which modifies the circuit structure of latch stage focuses on achieving a better performance of delay at the cost of a worse energy consumption relatively. Another innovative design of comparator that named as three-stage comparator adds an extra amplifier stage to solve the problems of noise and get a lower delay. Because of the additional preamplifier stage, the NMOS pair can be used in both the latch-stage and the first preamplifier stage, increasing speed. The performance of these three comparators are discussed in this paper and some schemes of comparator design are also presented.