A Method for Reducing Leakage Current of Static Logic Gates in 65nm CMOS Technology

Abstract:
Leakage current has a significant impact on power consumption in many contemporary high-performance systems. A new method for reducing leakage current and power is proposed in this paper. The main concept is to add two P-channel Metal Oxide Semiconductors (PMOS) and two N-channel Metal Oxide Semiconductors (NMOS) on the basis of the original logic circuit. One PMOS is added between the power supply and the pull-up network, and one NMOS is added between the pull-down network and the ground. Both of them are controlled by the input signal. While the other two PMOS and NMOS are added near the output terminal and are controlled by the voltage at different nodes along the powerto- ground path. Using this method, a NOT Gate is improved into three structures and simulated by Cadence Spectre with 65nm process transistors. The proposed method can reduce power consumption by up to 68.5% at 0-1V operating voltage. The design also has a full swing output, which ensures the normal operation of the logic system.