Tuning the parasitic JFET resistance for low on-state 1.2kV SiC power MOSFETs
Conference: PCIM Asia 2024 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
08/28/2024 - 08/30/2024 at Shenzhen, China
doi:10.30420/566414049
Proceedings: PCIM Asia 2024
Pages: 6Language: englishTyp: PDF
Authors:
Schneider, Nick; Diaz Reigosa, Paula; Stark, Roger; Schnell, Raffael; Li, Coris; Liang, Leon; Knoll, Lars
Abstract:
This paper presents a method for extracting the channel and parasitic resistances of small pitch planar 1.2 kV SiC power MOSFETs. In addition, the influence of channel width, cell pitch and JFET doping on the overall device performance is presented. By optimizing the device design and layout, excellent static and dynamic performance is achieved. Test substrates are used for static and dynamic characterization.