SiC MOSFET Reliability Assessment Under Accelerated Dynamic Reverse Bias Methodology.

Abstract:
This study examines the real-time reliability of commercial SiC MOSFETs by comparing three distinct 1.2 kV, 80 mOmega, ≥ 30 A technologies: asymmetric trench, symmetric trench, and planar structures. To ensure repeatability, two samples from each technology were subjected to distinctive electrothermal stress conditions designed to mimic real-world operation. These conditions included operation at over 75% of the device's measured breakdown voltage (BV) with controlled overshoot, high dv/dt at no-load conditions, and self-heating between 150deg C -180deg C under accelerated dynamic reverse bias (ADRB). Pre- and post-stress analyses revealed degradation across all devices. The 100h test (one cycle) proved to be highly effective in exposing degradation patterns that would otherwise require significantly longer and more complex testing mechanisms. It is observed that some parameters showed partial recovery after stress removal. However, this study highlights the non-recoverable drift or permanent shifts, un-derscoring the challenges in SiC MOSFET robustness under hard conditions. VTH exhibited the most significant positive drift, particularly in planar devices, followed by asymmetric and symmetric trench structures. Other key parameters, including RON, body-diode ‘VSD’, and IDS-VGS, also experienced notable shifts.