SmartSiC (TM) 150 & 200mm Engineered Substrate: Addressing Bipolar Degradation of SiC MOSFETs Body Diode
Conference: PCIM Conference 2025 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
05/06/2025 - 05/08/2025 at Nürnberg, Germany
doi:10.30420/566541201
Proceedings: PCIM Conference 2025
Pages: 5Language: englishTyp: PDF
Authors:
Guiot, Eric; Allibert, Frederic; Leib, Juergen; Becker, Tom; Bagchi, Rijuta; Gelineau, Guillaume; Barbet, Sophie; Lavieville, Romain; Godignon, Philippe; Schwarzenbach, Walter
Abstract:
The Smart Cut(TM) technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm2. A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm2 stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.