Impact of Gate Turn-off Voltage on Body Diode Degradation of the Latest Generation SiC MOSFET
Conference: PCIM Conference 2025 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
05/06/2025 - 05/08/2025 at Nürnberg, Germany
doi:10.30420/566541204
Proceedings: PCIM Conference 2025
Pages: 7Language: englishTyp: PDF
Authors:
Karout, Mohammed Amer; Haleem, Malik Abdul; Deb, Arkadeep; Arnold, Niamh; Renz, Arne Benjamin; Fisher, Craig; Jahdi, Saeed; Alatise, Olayiwola; Gammon, Peter
Abstract:
In this paper, the body diode degradation of the latest generation Trench and Planar SiC MOSFET is investigated against the gate turn-off voltage. In Trench MOSFETs, when negative gate turn-off voltage is used, experimental measurements reveal significant degradation in the device characteristics. After 96 h of DC current stress on the body diode, the device exhibits a 22.5% increase in on-state resistance, a 4.7% increase in the body diode voltage drop and an increase of over 150 nA in drain-source leakage current. In contrast, when the gate turn-off voltage is maintained at zero during the same stress period, degradation is significantly reduced, with only a ±2% variation in on-state resistance and less than a 2% increase in body diode voltage drop. Meanwhile, in Planar MOSFET, neither negative nor zero gate voltage conditions result in substantial changes in device characteristics, demonstrating the superior bipolar degradation ruggedness of the planar MOSFET compared to the Trench MOSFET.