Improving POL Thermal Cycling Reliability to 200deg.C through CTE Matching of Back Side Substrate

Abstract:
Power overlay (POL) is a wire bondless structure with copper vias joining on the top side of the devices, developed for the next generation power semiconductor. In this paper, we evaluated the thermal defor-mation and thermal cycling reliability of a back side substrate with different coefficients of thermal ex-pansion (CTE) joined with the POL. The results show that we confirmed significant reductions in thermal deformation through the combination of the POL with copper based insulating metal substrates (IMS) that have a similar CTE to the POL. Furthermore, the POL joined with IMS achieved reliability of 1750 cycles in thermal cycling up to 200 deg.C. The results show that POL has the heat resistance required for next-generation power semiconductor packages by further optimizing the package composition.