Optimization of semiconductor bare die positions within multi-chip power modules

Abstract:
Power modules are a key component in power electronic converters. The development of a power module is a multi-physics design problem. Depending on the area of operation and application the design requirements vary. Manual optimization by human developers is a time-consuming procedure with repetitive tasks. In this contribution, a workflow to automate the positioning process for bare dies within a multi-chip power module is presented. Data structures are proposed to describe the entire power module geometry. Additionally, automated 3D simulations in Ansys Q3D and Mechanical are implemented to evaluate designs based on electrical and thermal performance. This approach aims to accelerate the development process while reducing the workload.