Optimal Transistor Dimensioning in T-Type Topology for Reduced Quasi-2-Level Switching Loss

Abstract:
A quasi-2-level switching T-type topology reduces hard-switching loss compared to half-bridges, but requires more semiconductor area. This work shows that the middle transistor can be dimensioned smaller than the high/low-side transistors, which further reduces both the switch node capacitance and switching loss. The paper also presents a scalable transistor model, which is used in simulations of inductiveload hard-switching to determine switching losses and reveal a loss-optimal transistor dimensioning. Furthermore a double pulse setup (600 V-rated GaN HEMTs in a T-type topology) with 2 ground referenced shunts is proposed to determine switching energy of middle and low side transistors simultaneously. To verify the concept of loss-optimal transistor dimensioning in Q2L T-type topology, switching energy was measured at 200V and 1 A, with the middle transistors area reduced by half compared to high/low side, resulting in a measured reduction from 4.44 muJ to 2.18 muJ (-51%) which is similar to the simulated reduction (2.39 muJ to 1.43 muJ, -40%). This method allows reduction of Q2L switching-loss with optimal transistor area and can be used for a wide range of applications.