Device Screening Approach based on Genetic Algorithm for Parallel Connection of SiC MOSFET

Abstract:
Device parameter discrepancies in SiC MOSFETs remain significant due to the immaturity of SiC material and device manufacturing processes. This can potentially cause current or thermal imbalances among paralleled SiC MOSFETs in multichip power modules. To mitigate these imbalances among the paralleled chips, this paper proposes a device screening strategy based on a genetic algorithm. The objective of the proposed screening method is to achieve superior optimization by employing a global multi-parameter optimization approach to minimize parameter discrepancies among the specific paralleled chips, unlike traditional screening methods that typically categorize chips into several groups based on a rough criterion. Additionally, it utilizes nearly all viable dies on the wafer without compromising chip utilization, making it suitable for large-scale production rather than just laboratory testing. Furthermore, by adjusting the optimization objective, the proposed approach can adapt to various operating conditions. The screening methods based on the genetic algorithm is explained in detail. The effectiveness of the proposed approach as well as the genetic algorithm is verified by simulation and experimental results.