Effect of Variable Lateral Doping (VLD) on Avalanche Ruggedness Capability of SiC Power MOSFETs
Conference: PCIM Conference 2025 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
05/06/2025 - 05/08/2025 at Nürnberg, Germany
doi:10.30420/566541261
Proceedings: PCIM Conference 2025
Pages: 8Language: englishTyp: PDF
Authors:
Srivastava, Pallavi; Salvo, Luciano; Cascino, Salvatore; Pulvirenti, Mario; Zanetti, Edoardo; Nania, Massimo
Abstract:
This paper investigates the effect of integrating Variable Lateral Doping (VLD) edge termination technology on the avalanche ruggedness capability of Silicon Carbide (SiC) Power MOSFETs. The standard Unclamped Inductive Switching (UIS) test circuit is used to determine the avalanche ruggedness by emulating the catastrophic events that can occur during an abrupt turn-off of a MOSFET with an inductive load. TCAD models of SiC MOSFETs, both with and without VLD, are simulated with SILVACO suite to understand the impact of VLD on device performance. The simulation results are subsequently verified experimentally on 1200V SiC Power MOSFETs in a HiP247-4 package.