High Power Density Two-Level Switching Cells based on SiC MOSFET in Q-DPAK Top Side Cooled Package

Abstract:
High power density converters are an undeniable trend in power converters in the low-to-mid kW range. Top Side Cooled (TSC) Surface Mounted Devices (SMD) offer several advantages, like pick-and-place assembly and excellent electrical and thermal performance. Standard layout practices for TSC-SMD devices exist, however, for achieving the next level of power density, some topology-specific optimizations are possible. This article presents four high power-dense switching cells based on SiC MOSFETs housed in a Q-DPAK TSC package that have been optimized on the bases of clearance and creepage requirements, topology type (i.e. hard-switching or soft-switching), scalability, and the size of the magnetic components that will be used in conjunction with the switching cell (SW-Cell). Using a double pulse test (DPT), the SW-Cells’ external gate resistors values have been optimized, and the power loop inductance were extracted and compared with values extracted from a multiphysics parasitic extraction. We show that a power loop inductance of down to 7nH is possible in a half-bridge with TSC devices in the size of Q-DPAK. With these results, design guidelines are given to choose the optimal power loop.