Device Level Degradation Due to Power Cycling Test in SiC Power Module

Abstract:
This study examined whether SiC Trench MOSFET power modules could experience chip-level degradation due to bias temperature stress factors during Power Cycling Tests. IV characteristic curves and Gate Charge curves were measured for intrinsic and power cycled devices. These measurements were compared with results from Positive/Negative Bias Temperature Stress. The Transfer Curve shifted to the right, and the threshold voltage increased. In the Gate Charge curve, an increase in Miller Plateau Voltage was observed. These electrical characteristic changes correspond to those caused by Positive Bias Temperature Stress. The results demonstrate that power cycling tests can induce chip-level degradation to SiC power modules.