Impact of P-well Contact on Dynamic Losses in Scaled 1.2 kV SiC MOSFETs for Parallel Switching Applications

Abstract:
This paper presents a newly developed 1.2 kV planar-gate SiC MOSFETs featuring ultra short-channel and superior paralleling behavior. The key innovations include: (1) analysis of the P-well contact layout and its impact on both static and dynamic characteristics, (2) an on-state resistance with a weak positive temperature coefficient, resulting in lower conduction losses at high operating temperatures, and (3), a relatively high threshold voltage for improved short-circuit capability. To demonstrate reliable parallel operation, six devices were mounted into a Highly Efficient EV power module (HEEV) showing its performance under practical conditions.