DRAMPyML: A Formal Description of DRAM Protocols with Timed Petri Nets

Abstract:
The JEDEC committee defines various domainspecific DRAM standards. These standards feature increasingly complex protocol specifications, which are detailed in numerous timing diagrams and command tables. As new features and complex device hierarchies emerge, understanding these protocols becomes increasingly difficult without an expressive model. While each JEDEC standard features a simplified state machine, it fails to reflect the parallel operation of memory banks and is in itself insufficient for describing the complex DRAM protocol. In this paper, we present an evolved modeling approach based on timed Petri nets and Python as a programming language. This model provides a more accurate representation of DRAM protocols, making them easier to understand and directly executable, which enables the evaluation of interesting metrics and the verification of controller RTL models, DRAM logic and memory simulators.