Variability Reduction in RRAM through Device Stack Engineering

Abstract:
Resistive random-access memory (RRAM) is a leading candidate for next-generation non-volatile memory and neuromorphic computing systems, owing to its high density, low power consumption, and compatibility with CMOS technology. However, device-to-device and cycle-to-cycle variability, particularly in the SET voltage (VSET), can significantly degrade computational accuracy and reliability in both analog and digital RRAM-based operations. In this work, we investigate material stack engineering as a strategy to suppress VSET variability. Three RRAM stacks: Pt/TaOx/Ta/Pt, Pt/HfO2/TiOx/Ti/Pt, and Pt/TaOx/Ti/Pt were fabricated on a 180-nm CMOS platform. Statistical analysis reveals that introducing a thin Ti or TiOx interlayer at the electrode–oxide interface markedly reduces variability. The Pt/TaOx/Ti/Pt stack achieved the lowest coefficient of variation (5.9%), corresponding to a ~60% reduction compared to the baseline Pt/TaOx/Ta/Pt device. These results demonstrate that interface-engineered RRAM stacks can enable more stable switching, offering a viable pathway toward reliable and energy-efficient neuromorphic hardware.