Vision of the APECS Pilot Line

Abstract:
Heterogeneous Integration for Electronic Components and Systems and Advanced Packaging (APECS) is essential for the sovereignty and competitive advantage in areas such as telecommunications, high-performance computing (HPC), Artificial Intelligence/Machine Learning (AI/ML), sensor systems, medical & scientific instrumentation and industrial manufacturing in Europe. The goal of the APECS Pilot Line (APECS-PL) is to enable European users to benefit from chiplets of various technologies, from any supplier (European or international). The APECS pilot line will therefore offer necessary services, capabilities and training for European companies, especially SMEs, to integrate and package chiplets into novel electronic components and systems. The platform of capabilities to be developed will include novel characterization, quality assurance, testing & reliability (CTR) methodologies and a System-Technology Co-Design (STCO) framework to ensure quality, reliability and fast production ramp-up in collaborating manufacturing organizations. In this paper the motivation and the vision will be explained in details as future microelectronic systems will require higher levels of functionality that cannot be managed by a single chip, even if advanced System-on-Chip (SoC) concepts are applied. Instead of manufacturing one large semiconductor chip and then packaging it as single monolithic IC component, the IC is broken down into various smaller parts, chiplets. The assembly of these multiple small chiplets into a complex, and often three-dimensional package leads to highly integrated system components. Using a modular design, many individual solutions can be implemented by interconnecting different basic functionalities. Special functions, such as RF, optical, sensing or other structures can be manufactured using optimal technologies on external wafers and in different structure sizes. The chiplets in the APCES-PL will be connected on special substrates (e.g. Si, glass, or organic) side-side-by-side (called 2,5D) or stacked (called 3D). The APECS-PL will provide open access in accordance with the Chips Act requirements by providing support to integrated production facilities and open EU foundries, SMEs and startups, through preferential access to the new pilot line, as well as by ensuring access on fair terms for a wide range of users of the Union’s semiconductor ecosystem.