Advanced Packaging solutions for HPC, Communication and sensor modules enabled by APECS pilot line

Abstract:
During the start-up of the APECS Pilot Line, four application areas of advanced heterogeneous integration are addressed by the realization of demonstrators that highlight and evaluate the combined capabilities of the pan-European project partners. In this paper all four challenges in microelectronics will be addressed in detail: High Performance Computing (HPC): HPC is driven by bandwidth requirements to enable increasing computing performance. Two general approaches are suitable to meet these requirements: Increasing the frequency and using finer pitches to widen the interface. A combination of both is not excluded. Heterogenous integration is required to combine chiplets and high-end packaging technologies, like fine-pitch silicon interposers. For the HPC demonstrator System-Technology-Co-Design (STCO) concepts will be enabled to co-design and co-optimize the system along all components and the used range of integration technologies. Based on the requirements this will lead to a first-time right functionality from the design to manufacturing and followed by verification measurements to confirm simulations. Sensor-Integration: This demonstrator addresses the packaging and integration of multi-material sensor components, ranging from CMOS via Post-CMOS and C to III-V. Besides their material aspects, the sensor interfaces are to be adjusted in co-design with their heterogeneous system interposers and sensor frontends (digital and mixed signal) to enable cost-efficient chiplet integration for rapid development of sensor components in application relevant integration levels. The range of envisaged sensor components covers acoustic, optically active (light steering as well as detection) as well as gas- and magnetic-sensing chiplets. Photonic-Integration: For this demonstrator an InP EML array chiplet will be integrated with an InP-HBT EML driver chiplet on a common interposer and coupled to an optical fiber array. The electrical high-speed connection between EML 4-array and driver uses polymer-based RF flexlines. Therefore, the photonic integration pilot line capabilities will be proved with a hybrid integration of InP chiplets on an interposer with photonic wire bonds (PWB) for the optical fiber coupling to a glass-based connector. A hybrid integrated high shoreline density o-band 4 channel transmitter (4x200Gb/s) for I/O in HPC systems will be realized. RF-integration: For RF-integration three types of independent demonstrators will be developed: The first demonstrator will integrate InP chiplets on SiGe-BiCMOS as a D-Band transceiver. Secondly, by integration of mHEMT and SiGe-BiCMOS chiplets on Si-based interposer an H-Band transceiver for 6G will be demonstrated. Finally, a D-Band Radar and sensing module will be developed as two sub-parts of a third demonstrator. The last module consists of a Fan-out Wafer Level Package combining D-Band communication chiplets with radar TX/RX transceiver on RF-Glass Interposer with integrated antenna. Both parts will be connected by a flex-polymer bridge.