Steep slope cryogenic CMOS devices for quantum computing

Abstract:
Cryogenic CMOS with ultra-low power consumption is essential for quantum computing. However, conventional CMOS designed for room-temperature operation faces significant challenges in power reduction at cryogenic temperatures due to band-tail effects. In this work, we present strategies to mitigate these effects in SOI-based MOSFETs, enabling the realization of steep-slope transistors at cryogenic temperature. Our approach includes interface engineering to reduce interface states, source/drain engineering to improve junction steepness and minimize defects, and the implementation of a GAA nanowire architecture to enhance electrostatic control and screening. By these technologies, we demonstrate the feasibility of steep-slope MOSFETs optimized for cryogenic operation with a minimum subthreshold swing of 2.3 mV/dec at 5K, paving the way for more efficient cryo-CMOS circuits in quantum computing applications.