Systematic DfY of Analogue Building Blocks incorporating Trimming Algorithms

Konferenz: ANALOG '06 - 9. ITG/GMM-Fachtagung
27.09.2006 - 29.09.2006 in Dresden, Germany

Tagungsband: ANALOG '06

Seiten: 6Sprache: EnglischTyp: PDF

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Sobe, Udo; Graupner, Achim; Böhme, Enno (ZMD Zentrum Mikroelektronik Dresden AG, Grenzstraße 28, 01109 Dresden)

Designers frequently use trimming techniques for electrical networks to improve the accuracy of analogue and mixed-signal building blocks. This technique is practiced particularly for circuits which have to provide an electrical signal with a high absolute accuracy, i.e. voltage, current or frequency references. Trimming is used to increase production yield. The design, simulation and verification of the circuit including trim network and trim algorithm is a quite demanding task. To our knowledge, it is poorly supported by current EDA tools. This paper presents a flow to design the circuit part, trim network and trim algorithm together during the circuit design phase. Details are explained and various methods to simulate all three parts together are compared. Further, a procedure to generate trim tables automatically is presented. Prerequisites and limits are discussed and practical results are shown.