3D Integration of Power Semiconductor Devices based on Surface Bump Technology
Konferenz: CIPS 2008 - 5th International Conference on Integrated Power Electronics Systems
11.03.2008 - 13.03.2008 in Nuremberg, Germany
Tagungsband: CIPS 2008
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Mermet-Guyennet, Michel; Lasserre, Philippe; Saiz, José (ALSTOM Transport - Power Electronics Associated Research Laboratory (PEARL), France)
Castellazzi, Alberto (Swiss Federal Institute of Technology (ETH Zurich) – Integrated Systems Laboratory (IIS), Switzerland)
This work presents the prototype development and testing of a vertically integrated half-bridge switch, utilizing IGBTs and anti-parallel freewheeling diodes. Stacking of the semiconductor devices is based on the power bump technology, which consists essentially in the replacement of bond-wire interconnections between device surface and substrate with conductive solid elements (spheres or cylinders) directly connected to an upper substrate. This approach, already demonstrated in its surface (2D) version, is characterised, in particular, by enhanced integration levels with double-sided cooling of the chips; here, for the first time, it is extended to the vertical direction (3D), keeping all of its positive distinctive features.