Low-cost digital control for SMPS integration
Konferenz: CIPS 2008 - 5th International Conference on Integrated Power Electronics Systems
11.03.2008 - 13.03.2008 in Nuremberg, Germany
Tagungsband: CIPS 2008
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Lin-Shi, Xuefang; Allard, Bruno (AMPERE, CNRS UMR 5005, INSA Lyon, Villeurbanne, France)
Guo, Shuibao; Gao, Yanxia (Institute of Electrical and Control Engineering, Shanghai University, Shanghai, China)
Digital control is becoming a new trend in Switching Mode Power Supply (SMPS) development. This paper described a prototype implementation of a digital control solution prior to monolithic integration. An original algorithm, called RST, is used to obtain a better rejection of load variations and PWM noises than PID algorithms while keeping a good robustness. Sensitivity functions have been introduced that help tuning the algorithm coefficients. An FPGA implementation has been performed for the control of a 1MHz step-down voltage regulator. One challenge in design is to meet the output voltage accuracy, avoid the limit cycle phenomenon and reduce the high-frequency clock requirement. The choice and impact of fixed-point representation for the computation has been discussed. A 9-bit resolution DPWM is obtained using DLL function modules in FPGA and a half cycle counter. Experimental results proved the performance of the proposed digitally control SMPS.